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| ? 2003 microchip technology inc. ds20090b-page 1 m mcp23016 features ? 16-bit remote bidirectional i/o port - 16 i/o pins default to 16 inputs ?fast i 2 c? bus clock frequency (0 - 400 kbits/s) ? three hardware address pins allow use of up to eight devices ? high-current drive capability per i/o: 25 ma ? open-drain interrupt output on input change ? interrupt port capture register ? internal power-on reset (por) ? polarity inversion register to configure the polarity of the input port data ? compatible with most microcontrollers ? available temperature range: - industrial (i): -40c to +85c cmos technology ? operating supply voltage: 2.0v to 5.5v ? low standby current packages ? 28-pin pdip, 300 mil; 28-pin soic, 300 mil ? 28-pin ssop, 209 mil; 28-pin qfn, 6x6 mm package types block diagram vss gp1.0 gp1.1 gp1.2 gp1.3 int gp1.4 v ss clk tp gp1.5 gp1.6 gp1.7 scl gp0.7 gp0.6 gp0.5 gp0.4 gp0.3 gp0.2 gp0.1 gp0.0 v dd v ss a2 a1 a0 sda ? 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pdip, soic, ssop qfn 2 3 4 5 6 1 7 gp1.2 gp1.3 int gp1.4 v ss clk tp 15 16 17 18 19 20 21 gp0.3 gp0.2 gp0.1 gp0.0 v dd v ss a2 gp1.5 gp1.6 gp1.7 scl sda a0 a1 23 24 25 26 27 28 22 gp1.1 gp1.0 vss gp0.7 gp0.6 gp0.5 gp0.4 1011 8 9 121314 mcp23016 mcp23016 16 bits gp0.0 to gp0.7 gp1.0 to gp1.7 write pulse read pulse low pass filter interrupt logic i 2 c? bus control address decoder power-on reset i/o port deserializer serializer/ control clock gen i 2 c? bus interface/ protocol handler int a0 a1 a2 scl sda clkin v dd v ss configuration registers control 8-bit tp iares 16-bit i 2 c ? i/o expander
mcp23016 ds20090b-page 2 ? 2003 microchip technology inc. notes: ? 2003 microchip technology inc. ds20090b-page 3 mcp23016 1.0 device overview the mcp23016 device provides 16-bit, general purpose, parallel i/o expansion for i 2 c bus applications. this device includes high-current drive capability, low supply current and individual i/o configuration. i/o expanders provide a simple solution when additional i/os are needed for acpi, power switches, sensors, push buttons, leds and so on. the mcp23016 consists of multiple 8-bit configuration registers for input, output and polarity selection. the system master can enable the i/os as either inputs or outputs by writing the i/o configuration bits. the data for each input or output is kept in the corresponding input or output register. the polarity of the read register can be inverted with the polarity inversion register (see section 1.7.3, ?input polarity registers? ). all registers can be read by the system master. the open-drain interrupt output is activated when any input state differs from its corresponding input port register state. this is used to indicate to the system master that an input state has changed. the interrupt capture register captures port value at this time. the power-on reset sets the registers to their default val- ues and initializes the device state machine. three device inputs (a0 - a2) determine the i 2 c address and allow up to eight i/o expander devices to share the same i 2 c bus. 1.1 pin descriptions table 1-1: pinout description pin name pdip, soic, ssop pin no. qfn pin no. i/o/p type buffer type description clk 9 6 i st clock source input tp 10 7 o ? test pin (this pin must be left floating) gp1.0 2 27 i/o ttl d0 digital input/output for gp1 gp1.1 3 28 i/o ttl d1 digital input/output for gp1 gp1.2 4 1 i/o ttl d2 digital input/output for gp1 gp1.3 5 2 i/o ttl d3 digital input/output for gp1 gp1.4 7 4 i/o ttl d4 digital input/output for gp1 gp1.5 11 8 i/o st d5 digital input/output for gp1 gp1.6 12 9 i/o st d6 digital input/output for gp1 gp1.7 13 10 i/o st d7 digital input/output for gp1 gp0.0 21 18 i/o ttl d0 digital input/output for gp0 gp0.1 22 19 i/o ttl d1 digital input/output for gp0 gp0.2 23 20 i/o ttl d2 digital input/output for gp0 gp0.3 24 21 i/o ttl d3 digital input/output for gp0 gp0.4 25 22 i/o ttl d4 digital input/output for gp0 gp0.5 26 23 i/o ttl d5 digital input/output for gp0 gp0.6 27 24 i/o ttl d6 digital input/output for gp0 gp0.7 28 25 i/o ttl d7 digital input/output for gp0 scl 14 11 i st serial clock input sda 15 12 i/o st serial data i/o int 6 3 o od interrupt output a0 16 13 i st address input 1 a1 17 14 i st address input 2 a2 18 15 i st address input 3 v ss 1, 8, 19 5, 16, 26 p ? ground reference for logic and i/o pins v dd 20 17 p ? positive supply for logic and i/o pins mcp23016 ds20090b-page 4 ? 2003 microchip technology inc. 1.2 power-on reset (por) the on-chip por circuit holds the chip in reset until v dd has reached a high enough level to deactivate the por circuit (i.e., release reset). a maximum rise time for v dd is specified in the electrical specifications. when the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature) must be met to ensure proper operation. 1.3 power-up timer (pwrt) the power-up timer provides a 72 ms nominal time- out on power-up, keeping the device in reset and allowing v dd to rise to an acceptable level. the power-up time delay will vary from chip-to-chip due to v dd , temperature and process variation. see table 2-4 for details (t pwrt , parameter 3). 1.4 clock generator the mcp23016 uses an external rc circuit to determine the internal clock speed. the user must connect r and c to the mcp23016, as shown in figure 1-1. figure 1-1: clock configuration a 1 mhz (typ.) internal clock is needed for the device to function properly. the internal clock can be measured on the tp pin. recommended r ext and c ext values are shown in table 1-2. 1.5 i 2 c bus interface/ protocol handler this block manages the functionality of the i 2 c bus interface and protocol handling. the mcp23016 supports the following commands: table 1-3: command byte to register relationship 1.6 address decoder the last three lsb of the 7-bit address are user-defined (see table 1-4). three hardware pins ( ? 2003 microchip technology inc. ds20090b-page 5 mcp23016 1.7 register block the register block contains the configuration and port registers, as shown in table 1-5. table 1-5: register summary name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por port registers gp0 gp0.7 gp0.6 gp0.5 gp0.4 gp0.3 gp0.2 gp0.1 gp0.0 0000 0000 gp1 gp1.7 gp1.6 gp1.5 gp1.4 gp1.3 gp1.2 gp1.1 gp0.0 0000 0000 olat0 ol0.7 ol0.6 ol0.5 ol0.4 ol0.3 ol0.2 ol0.1 ol0.0 0000 0000 olat1 ol1.7 ol1.6 ol1.5 ol1.4 ol1.3 ol1.2 ol1.1 ol1.0 0000 0000 configuration registers ipol0 igp0.7 igp0.6 igp0.5 igp0.4 igp0.3 igp0.2 igp0.1 igp0.0 0000 0000 ipol1 igp1.7 igp1.6 igp1.5 igp1.4 igp1.3 igp1.2 igp1.1 igp1.0 0000 0000 iodir0 iod0.7 iod0.6 iod0.5 iod0.4 iod0.3 iod0.2 iod0.1 iod0.0 1111 1111 iodir1 iod1.7 iod1.6 iod1.5 iod1.4 iod1.3 iod1.2 iod1.1 iod1.0 1111 1111 intcap0 icp0.7 icp0.6 icp0.5 icp0.4 icp0.3 icp0.2 icp0.1 icp0.0 xxxx xxxx intcap1 icp1.7 icp1.6 icp1.5 icp1.4 icp1.3 icp1.2 icp1.1 icp1.0 xxxx xxxx iocon0 ? ? ? ? ? ? ? iares ---- ---0 iocon1 ? ? ? ? ? ? ? iares ---- ---0 legend: ? 1? bit is set, ?0? bit is cleared, x = unknown, ? = unimplemented. mcp23016 ds20090b-page 6 ? 2003 microchip technology inc. 1.7.1 data port registers two registers provide access to the two gpio ports: ? gp0 (provides access to data port gp0) ? gp1 (provides access to data port gp1) a read from this register provides status on pins of these ports. a write to these registers will modify the output latch registers (olat0, olat1) and data output. register 1-1: gp0 - general purpose i/o port register 0 register 1-2: gp1 - general purpose i/o port register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gp0.7 gp0.6 gp0.5 gp0.4 gp0.3 gp0.2 gp0.1 gp0.0 bit 7 bit 0 bit 7-0 gp0.0:gp0.7 : reflects the logic level on the pins. 1 = logic ? 1 ? 0 = logic ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gp1.7 gp1.6 gp1.5 gp1.4 gp1.3 gp1.2 gp1.1 gp1.0 bit 7 bit 0 bit 7-0 gp1.0:gp1.7 : reflects the logic level on the pins. 1 = logic ? 1 ? 0 = logic ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown ? 2003 microchip technology inc. ds20090b-page 7 mcp23016 1.7.2 output latch registers two registers provide access to the two port output latches: ? olat0 (provides access to the output latch for port gp0) ? olat1 (provides access to the output latch for port gp1) a read from these registers results in a read of the latch that controls the output and not the actual port. a write to these registers updates the output latch that controls the output. register 1-3: olat0 - output latch register 0 register 1-4: olat1 - output latch register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ol0.7 ol0.6 ol0.5 ol0.4 ol0.3 ol0.2 ol0.1 ol0.0 bit 7 bit 0 bit 7-0 ol0.0:o0.7 : reflects the logic level on the output latch. 1 = logic ? 1 ? 0 = logic ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ol1.7 ol1.6 ol1.5 ol1.4 ol1.3 ol1.2 ol1.1 ol1.0 bit 7 bit 0 bit 7-0 ol1.0:o1.7 : reflects the logic level on the output latch. 1 = logic ? 1 ? 0 = logic ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown mcp23016 ds20090b-page 8 ? 2003 microchip technology inc. 1.7.3 input polarity registers these registers allow the user to configure the polarity of the input port data (gp0 and gp1). if a bit in this reg- ister is set, the corresponding input port (gpn) data bit polarity will be inverted. ? ipol0 (controls the polarity of gp0) ? ipol1 (controls the polarity of gp1) register 1-5: ipol0 - input polarity port register 0 register 1-6: ipol1 - input polarity port register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 igp0.7 igp0.6 igp0.5 igp0.4 igp0.3 igp0.2 igp0.1 igp0.0 bit 7 bit 0 bit 7-0 igp0.0:igp0.7 : controls the polarity inversion for the input pins 1 = corresponding gp0 bit is inverted 0 = corresponding gp0 bit is not inverted legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 igp1.7 igp1.6 igp1.6 igp1.4 igp1.3 igp1.2 igp1.1 igp1.0 bit 7 bit 0 bit 7-0 igp1.0:igp1.7 : controls the polarity inversion for the input pins 1 = corresponding gp1 bit is inverted 0 = corresponding gp1 bit is not inverted legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown ? 2003 microchip technology inc. ds20090b-page 9 mcp23016 1.7.4 i/o direction registers two registers control the direction of data i/o: ? iodir0 (controls gp0) ? iodir1 (controls gp1) when a bit in these registers is set, the corresponding pin becomes an input. otherwise, it becomes an output. at power-on reset, the device ports are configured as inputs. register 1-7: iodir0 - i/o direction register 0 register 1-8: iodir1 - i/o direction register 1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 iod0.7 iod0.6 iod0.5 iod0.4 iod0.3 iod0.2 iod0.1 iod0.0 bit 7 bit 0 bit 7-0 iod0.0:io0.7: controls the direction of data i/o 1 = input 0 = output legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 iod1.7 iod1.6 iod1.5 iod1.4 iod1.3 iod1.2 iod1.1 iod1.0 bit 7 bit 0 bit 7-0 iod1.0:io1.7: controls the direction of data i/o 1 = input 0 = output legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown mcp23016 ds20090b-page 10 ? 2003 microchip technology inc. 1.7.5 interrupt capture registers two registers contain the value of the port that generated the interrupt: ? intcap0 contains the value of gp0 at time of gp0 change interrupt ? intcap1 contains the value of gp1 at time of gp1 change interrupt these registers are ?read-only? registers (a write to these registers is ignored). register 1-9: intcap0 - interrupt captured value for port register 0 register 1-10: intcap1 - interrupt captured value for port register 1 r-x r-x r-x r-x r-x r-x r-x r-x icp0.7 icp0.6 icp0.5 icp0.4 icp0.3 icp0.2 icp0.1 icp0.0 bit 7 bit 0 bit 7-0 icp0.0:icp0.7: reflects the logic level on the gp0 pins at the time of interrupt due to pin change 1 = logic ? 1 ? 0 = logic ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown r-x r-x r-x r-x r-x r-x r-x r-x icp1.7 icp1.6 icp1.5 icp1.4 icp1.3 icp1.2 icp1.1 icp1.0 bit 7 bit 0 bit 7-0 icp1.0:icp1.7: reflects the logic level on the gp1 pins at the time of interrupt due to pin change 1 = logic ? 1 ? 0 = logic ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown ? 2003 microchip technology inc. ds20090b-page 11 mcp23016 1.7.6 i/o expander control register ? iocon0 controls the functionality of the mcp23016. the iares (interrupt activity resolution) bit controls the sampling frequency of the gp port pins. the higher the sampling frequency, the higher the device current requirements. if this bit is ? 0 ? (default), the maximum time to detect the activity on the port is 32 ms (max.), which results in lower standby current. if this bit is ? 1 ?, the maximum time to detect activity on the port is 200 sec. (max.) and results in higher standby current. register 1-11: iocon0 - i/0 expander control register u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ? iares bit 7 bit 0 bit 1-7 unimplemented bit: read as ?0? bit 0 iares : interrupt activity resolution 1 = fast sample rate 0 = normal sample rate legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown iocon1 is a shadow register for iocon0. access to iocon1 results in access to iocon0. mcp23016 ds20090b-page 12 ? 2003 microchip technology inc. 1.8 serializer/deserializer the serializer/deserializer block converts and transfers data between the i 2 c bus and gpio. 1.9 interrupt logic the mcp23016 asserts the open-drain interrupt output (int ) low when one of the port pins changes state. only those pins that are configured as an input can cause an interrupt. pins defined as an output have no effect on int. the interrupt will remain active until a read from either the port (gpn) on which the interrupt occurred or the intcapn register is performed. if the input returns to its previous state before a read operation, it will reset the interrupt and the int pin output will tri-state. each 8-bit port is read separately, so reading gp0 or intcap0 will not clear the interrupt generated by gp1 or intcap1, and vice versa. input change activity on each port will generate an interrupt and the value of the particular port will be captured and copied into intcap0/intcap1. the intcapn registers are only updated when an interrupt occurs on int . these values will stay unchanged until the user clears the interrupt by reading the port or the intcapn register. if the input port value changes back to normal before a user-read, the int output will be reset. however, the intcap0/intcap1 will still contain the value of the port at the interrupt change. if the port value changes again, it will re-activate the interrupt and the new value will be captured. the first interrupt on change event following an interrupt reset will result in a capture event. any fur- ther change event that occurs before the interrupt is reset will not result in a capture event. 1.9.1 interrupt event detection the iares bit controls the resolution for detecting an interrupt-on-change event. if this bit is ? 0 ? (default), the maximum time for detecting a change of event is high, which results in lower standby current. if this bit is ? 1 ?, it takes less time for scanning the activity on the port and results in higher standby current. figure 1-2: reading portx after interrupt event port value port x port x gpx int is captured and written to intcapn port value is captured and written to intcapn read gpx or intcapn ? 2003 microchip technology inc. ds20090b-page 13 mcp23016 1.9.2 writing the registers to write to a mcp23016 register, the master i 2 c device needs to follow the requirements, as illustrated in figure 1-3. first, the device is selected by sending the slave address and setting the r/w bit to logic ? 0 ?. the command byte is sent after the address and determines which register will be written. table 1-3 shows the relationship of the command byte and register. the mcp23016 has twelve 8-bit registers. they are configured to operate as six 16-bit register pairs, supporting the device?s 16-bit port. these pairs are formed based on their functions (e.g., gp0 and gp1 are grouped together). the i 2 c commands apply to one register pair to provide faster access. the first data byte following a command byte is written into the register pointed to by the command byte, while the second data is written into another register in the same pair. for example, if the first byte is sent to olat1 (command byte 03h ), the next data byte will be written into the second register of that pair, olat0. if the first byte is written to olat0 (command byte 02h ), the second byte will be written to olat1. there is no limitation on the number of data bytes in one write transmission. figure 1-4 shows the case of multiple byte writes in one write operation. in this case, the multiple writes are made to the same data pair. figure 1-3: write to configuration registers (case 1) note: the bus must remain free until after the ninth clock pulse for a minimum of 12 s (see table 2-5 and figure 2-4). 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 a2 a1 a0 d0 s 0 r/w =0 ack d6 d5 d4 d3 d2 d1 d7 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 d0 d6 d5 d4 d3 d2 d1 d7 ack d0 d6 d5 d4 d3 d2 d1 d7 ack p address command byte data 1 data 2 ack scl held low until data is processed mcp23016 ds20090b-page 14 ? 2003 microchip technology inc. figure 1-4: write to configuration registers (case 2) figure 1-5: write to output ports 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 a2 a1 a0 d0 s 0 r/w =0 ack d6 d5 d4 d3 d2 d1 d7 ack 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 d0 d6 d5 d4 d3 d2 d1 d7 ack d0 d6 d5 d4 d3 d2 d1 d7 ack address command byte data 1 data 2 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 d0 d6 d5 d4 d3 d2 d1 d7 ack d0 d6 d5 d4 d3 d2 d1 d7 ack p data 1 data 2 scl held low until data is processed scl held low until data is processed 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 a2 a1 a0 d0 s 0 r/w =0 ack d6 d5 d4 d3 d2 d1 d7 ack 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 d0 d6 d5 d4 d3 d2 d1 d7 ack d0 d6 d5 d4 d3 d2 d1 d7 ack p address command byte data 1 data 2 data valid t gpv0 data valid t gpv1 sda scl data on gp0 data on gp1 scl held low until data is processed ? 2003 microchip technology inc. ds20090b-page 15 mcp23016 1.9.3 reading the registers to read a mcp23016 register, the master needs to follow the requirements shown in figure 1-6. first, the device is selected by sending the slave address and setting the r/w bit to logic ? 0 ?. the command byte is sent after the address and determines which register will be read. a restart condition is generated and the device address is sent again with the r/w bit set to logic ? 1 ?. the data register defined by the command byte will be sent first, followed by the other register in the register pair. the logic for register selection is the same as explained in write mode ( section 1.9.2, ?writing the registers? ). the falling edge of the ninth clock initiates the register read action. the scl clock will be held low while the data is read from the register and is transferred to the i 2 c bus control block by the serializer/deserializer block. the mcp23016 holds the clock low after the falling edge of the ninth clock pulse. the configuration registers (or port control registers) are read and the value is stored. finally, the clock is released to enable the next transmission. there is no limitation on the number of data bytes in one read transmission. figure 1-8 shows the case of multiple byte read in one read operation. in this case, the multiple writes are made to the same data pair. figure 1-6: read from configuration register note: the bus must remain free until after the ninth clock pulse for a minimum of 12 s (see table 2-5 and figure 2-4). 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 a2 a1 a0 d0 s 0 r/ w =0 ack d6 d5 d4 d3 d2 d1 d7 ack address command byte 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 a2 a1 a0 d0 s 0 r/ w =0 ack d6 d5 d4 d3 d2 d1 d7 ack address data from lsb or msb of register 1 2 3 4 5 6 7 8 9 d0 d6 d5 d4 d3 d2 d1 d7 ack data from msb or lsb of register p sda scl scl held low until data is processed scl held low until data is processed 0 mcp23016 ds20090b-page 16 ? 2003 microchip technology inc. figure 1-7: read from input ports (case 1) note: it is assumed that command byte is already set to ? 00 ?. 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 a2 a1 a0 d0 s 0 r/w =0 ack d6 d5 d4 d3 d2 d1 d7 ack address data from lsb or msb of register 1 2 3 4 5 6 7 8 9 d0 d6 d5 d4 d3 d2 d1 d7 ack data from msb or lsb of register p read signal (internal) for gp0 read signal (internal) for gp1 t rdd0 t rdd1 t icd0 t isd t icd1 data in gp0 data in gp1 int sda scl scl held low until data is processed ? 2003 microchip technology inc. ds20090b-page 17 mcp23016 figure 1-8: read from input ports (case 2) 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 a2 a1 a0 d0 s 0 r/w =0 ack d6 d5 d4 d3 d2 d1 d7 ack address data from gp0 1 2 3 4 5 6 7 8 9 d0 d6 d5 d4 d3 d2 d1 d7 ack data from gp1 1 2 3 4 5 6 7 8 9 d0 d6 d5 d4 d3 d2 d1 d7 ack data from gp0 1 2 3 4 5 6 7 8 9 d0 d6 d5 d4 d3 d2 d1 d7 ack data from gp1 p note: it is assumed that command byte is already set to 00. sda scl mcp23016 ds20090b-page 18 ? 2003 microchip technology inc. notes: ? 2003 microchip technology inc. ds20090b-page 19 mcp23016 2.0 electrical characteristics absolute maximum ratings ? ambient temperature under bias................................................................................................. ............... -55 to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on any pin with respect to v ss ......................................................................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +6.5v total power dissipation (note 1) ............................................................................................................................ 1 .0 w maximum current out of v ss pin .......................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... .. 250 ma input clamp current, i ik (v i < 0, or v i > v dd ) ....................................................................................................... 20 ma output clamp current, i ok (v o < 0, or v o > v dd ) ................................................................................................ 20 ma maximum output current sunk by any i/o pin..................................................................................... .................... 25 ma maximum output current sourced by any i/o pin .................................................................................. ................. 25 ma maximum current sunk by combined ports ...................................................................................................... 200 ma maximum current sourced by combined ports ..................................................................................... ........... 200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - i oh } + {(v dd -v oh ) x i oh } + (v o l x i ol ) ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. mcp23016 ds20090b-page 20 ? 2003 microchip technology inc. 2.1 dc characteristics table 2-1: dc characteristics dc characteristics standard operating conditions (unless otherwise stated) operating temperature: -40c t a +85c for industrial param no. characteristic sym min typ? max units conditions d001 supply voltage v dd 2.0 ? 5.5 v d002 standby current i dd ? 0.4 ma iares = 1 d003 standby current i pd ? 25 a iares = 0 input low voltage i/o ports v il d004 ttl buffer vss ? 0.15 v dd v for entire v dd range d004a vss ? 0.8v 4.5v v dd 5.5v d005 schmitt trigger buffer vss ? 0.2 v dd v input high voltage i/o ports v ih ? d006 ttl buffer 2.0 ? v dd v4.5v v dd 5.5v d006a 0.25 v dd + 0.8v ?v dd v for entire v dd range d007 schmitt trigger buffer 0.8 v dd ?v dd v for entire v dd range input leakage current d008 i/o ports i il ?? 1.0 a vss v pin v dd , pin at hi-impedance d009 clk ? ? 5.0 a vss v pin v dd output low voltage d010 i/o ports v ol ??0.6vi ol = 8.5 ma, v dd = 4.5v output high voltage d010 i/o ports v oh v dd -0.7 ? ? v i oh = 3.0 ma, v dd = 4.5v d011 v dd start voltage to ensure internal por signal v por ?vss? v d012 v dd rise rate to ensure internal por signal s vdd 0.05 - ? v/ms note 1 dc trip point v tpor 1.5 1.7 1.9 v dc slow ramp d012 v dd rise rate to ensure internal por signal with pwrt enabled s vdd 0.05 ? ? v/ms note 1 dc current draw i por ? 5.0 ? a at 5.0v (1 /volt typical) note 1: these parameters are characterized but not tested. 2: data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. 3: standby current is measured with all i/o in hi-impedance state and tied to v dd and v ss . 4: for rc clk, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2 r ext (ma) with r ext in kohm. 5: negative current is defined as coming out of the pin. ? 2003 microchip technology inc. ds20090b-page 21 mcp23016 figure 2-1: response time table 2-2: response time figure 2-2: test point clock timing table 2-3: test point clock timing table 2-4: power-up timer requirements v dd 1 parameter no. symbol characteristic min typ? max units conditions 1 response time 100 ? ? ns minimum time where a v dd transition from 5.0v to 0.0v to 5.0v will cause a r eset. all times less than 100 ns will be filtered. parameter no. symbol characteristic min typ ? max units conditions f tp tp pin frequency ? 1.0 ? mhz measured at tp pin, iares = ? 1 ?. 2 t tp tp pin clk period ? 1.0 ? s measured at tp pin, iares = ? 1 ?. ? data in "typ" column is at 5v, +25c unless otherwise stated. these parameters are for design guidance only and are not tested. t tp 2 parameter no. symbol characteristic min typ ? max units conditions 3t pwrt power-up timer period ? 72 ? ms ? data in "typ" column is at 5v, +25c unless otherwise stated. these parameters are for design guidance only and are not tested. mcp23016 ds20090b-page 22 ? 2003 microchip technology inc. figure 2-3: i 2 c bus start/stop bits timing table 2-5: i 2 c bus start/stop bits requirements param no. symbol characteristic min ty p max unit s conditions 90 t su : sta start condition 100 khz mode 4700 ? ? ns only relevant for repeated start condition (note 1) setup time 400 khz mode 600 ? ? 91 t hd : sta start condition 100 khz mode 4000 ? ? ns after this period, the first clock pulse is generated (note 1) hold time 400 khz mode 600 ? ? 92 t su : sto stop condition 100 khz mode 4700 ? ? ns setup time 400 khz mode 600 ? ? 93 t hd : sto stop condition 100 khz mode 4000 ? ? ns hold time 400 khz mode 600 ? ? note 1: these parameters are characterized but not tested. 91 92 93 scl sda start condition stop condition 90 ? 2003 microchip technology inc. ds20090b-page 23 mcp23016 figure 2-4: i 2 c bus data timing 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out 111 mcp23016 ds20090b-page 24 ? 2003 microchip technology inc. table 2-5: i 2 c bus data requirements param no. symbol characteristic min max units conditions 100 t high clock high time 100 khz mode 4.0 ? s (note 1) 400 khz mode 0.6 ? s 101 t low clock low time 100 khz mode 4.7 ? s (note 1) 400 khz mode 1.3 ? s 102 t r sda and scl rise time 100 khz mode ? 1000 ns (note 1) 400 khz mode 20 + 0.1 c b 300 ns c b is specified to be from 10 - 400 pf 103 t f sda and scl fall time 100 khz mode ? 300 ns (note 1) 400 khz mode 20 + 0.1 c b 300 ns c b is specified to be from 10 - 400 pf 90 t su : sta start condition setup time 100 khz mode 4.7 ? s only relevant for repeated start condition (note 1) 400 khz mode 0.6 ? s 91 t hd : sta start condition hold time 100 khz mode 4.0 ? s after this period, the first clock pulse is generated (note 1) 400 khz mode 0.6 ? s 106 t hd : dat data input hold time 100 khz mode 0 ? ns (note 1) 400 khz mode 0 0.9 s 107 t su : dat data input setup time 100 khz mode 250 ? ns (note 1) (note 3) 400 khz mode 100 ? ns 92 t su : sto stop condition setup time 100 khz mode 4.7 ? s (note 1) 400 khz mode 0.6 ? s 109 t aa output valid from clock 100 khz mode ? 3500 ns (note 1) (note 2) 400 khz mode ? ? ns 110 t buf bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmis- sion can start (note 1) 400 khz mode 1.3 ? s c b bus capacitive loading ? 400 pf 111 t wait clock wait time after ninth pulse 100 khz mode 12 s ? s time the bus must remain free after the ninth clock pulse before a new transmission can start. 400 khz mode 12 s ? s note 1: these parameters are characterized but not tested. 2: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 3: a fast mode (400 khz) i 2 c bus device can be used in a standard mode (100 khz) i 2 c bus system, but the requirement t su : dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max.+t su : dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification), before the scl line is released. ? 2003 microchip technology inc. ds20090b-page 25 mcp23016 table 2-7: gp0 and gp1 timing requirements param no. symbol characteristic min typ. max units conditions t gpv0 gp0 output data valid time ?40?stp = 1mhz t gpv1 gp1 output data valid time ?50?s t rdd0 gp0 data read delay time ?40?s t rdd1 gp1 data read delay time ?50?s t isd0 gp0 interrupt set delay time ? ? 200 s iares = 1, tp = 1 mhz ? ? 32 ms iares = 0, tp = 1 mhz t isd1 gp1 interrupt set delay time ? ? 200 s iares = 1, tp = 1 mhz ? ? 32 ms iares = 0, tp = 1 mhz t lcd0 gp0 interrupt clear delay time (for read) ? 100 ? s tp = 1 mhz t lcd1 gp1 interrupt clear delay time (for read) ? 100 ? s note 1: these parameters are characterized but not tested. mcp23016 ds20090b-page 26 ? 2003 microchip technology inc. figure 2-5: gp0 and gp1 port timings note: it is assumed that command byte is already set to ?00?. 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 a2 a1 a0 d0 s 0 r/w =0 ack d6 d5 d4 d3 d2 d1 d7 ack address data from lsb or msb of register 1 2 3 4 5 6 7 8 9 d0 d6 d5 d4 d3 d2 d1 d7 ack data from msb or lsb of register p read signal(internal) for gp0 read signal(internal) for gp1 t rdd0 t rdd1 t icd0 t isd t icd1 data in gp0 data in gp1 int sda scl scl held low until data is processed ? 2003 microchip technology inc. ds20090b-page 27 mcp23016 3.0 package information 3.1 package marking information 28-lead soic yywwnnn example: xxxxxxxxxxxxxxxxx yywwnnn 28-lead pdip (skinny dip) example: xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx 0317017 mcp23016 -i/sp 0310017 mcp23016 -i/so 28-lead ssop yywwnnn xxxxxxxxxxxx xxxxxxxxxxxx example: 0320017 mcp23016 28-lead qfn example: xxxxxxxx xxxxxxxx yywwnnn 1 mcp23016 -i/ml 0310017 1 -i/ss legend: xx...x customer specific information* y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard marking consists of microchip part number, year code, week code, and traceability code. please check with your microchip sales office. mcp23016 ds20090b-page 28 ? 2003 microchip technology inc. 28-lead skinny plastic dual in-line (sp) ? 300 mil (pdip) 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 10.92 8.89 8.13 .430 .350 .320 eb overall row spacing 0.56 0.48 0.41 .022 .019 .016 b lower lead width 1.65 1.33 1.02 .065 .053 .040 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.18 .135 .130 .125 l tip to seating plane 35.18 34.67 34.16 1.385 1.365 1.345 d overall length 7.49 7.24 6.99 .295 .285 .275 e1 molded package width 8.26 7.87 7.62 .325 .310 .300 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.43 3.30 3.18 .135 .130 .125 a2 molded package thickness 4.06 3.81 3.56 .160 .150 .140 a top to seating plane 2.54 .100 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n e1 c eb e p l a2 b b1 a a1 notes: jedec equivalent: mo-095 drawing no. c04-070 * controlling parameter dimension d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. significant characteristic ? 2003 microchip technology inc. ds20090b-page 29 mcp23016 28-lead plastic small outline (so) ? wide, 300 mil (soic) foot angle top 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.33 0.28 0.23 .013 .011 .009 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.74 0.50 0.25 .029 .020 .010 h chamfer distance 18.08 17.87 17.65 .712 .704 .695 d overall length 7.59 7.49 7.32 .299 .295 .288 e1 molded package width 10.67 10.34 10.01 .420 .407 .394 e overall width 0.30 0.20 0.10 .012 .008 .004 a1 standoff 2.39 2.31 2.24 .094 .091 .088 a2 molded package thickness 2.64 2.50 2.36 .104 .099 .093 a overall height 1.27 .050 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 l c 45 h a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-013 drawing no. c04-052 significant characteristic mcp23016 ds20090b-page 30 ? 2003 microchip technology inc. 28-lead plastic shrink small outline (ss) ? 209 mil, 5.30 mm (ssop) * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-150 drawing no. c04-073 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.38 0.32 0.25 .015 .013 .010 b lead width 203.20 101.60 0.00 8 4 0 foot angle 0.25 0.18 0.10 .010 .007 .004 c lead thickness 0.94 0.75 0.56 .037 .030 .022 l foot length 10.34 10.20 10.06 .407 .402 .396 d overall length 5.38 5.25 5.11 .212 .207 .201 e1 molded package width 8.10 7.85 7.59 .319 .309 .299 e overall width 0.25 0.15 0.05 .010 .006 .002 a1 standoff 1.83 1.73 1.63 .072 .068 .064 a2 molded package thickness 1.98 1.85 1.73 .078 .073 .068 a overall height 0.65 .026 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters* inches units 2 1 d p n b e1 e l c a2 a1 a significant characteristic ? 2003 microchip technology inc. ds20090b-page 31 mcp23016 28-lead plastic quad flat no leads package (ml) 6x6 mm body (qfn) lead width * controlling parameter notes: mold draft angle top b .009 12 .011 .014 0.23 12 0.28 0.35 d pitch number of pins overall width standoff molded package length overall length molded package width molded package thickness overall height max units dimension limits a2 a1 e1 d d1 e n p a .026 .236 bsc .000 .226 bsc inches .026 bsc min 28 nom max 0.65 .031 .002 0.00 6.00 bsc 5.75 bsc millimeters* .039 min 28 0.65 bsc nom 0.80 0.05 1.00 e e1 n 1 2 d1 a a2 exposed metal pad s bottom view .008 ref. base thickness a3 0.20 ref. top view 0.85 .033 .0004 0.01 .236 bsc .226 bsc 6.00 bsc 5.75 bsc q l lead length tie bar width l .020 .024 .030 0.50 0.60 0.75 r .005 .007 .010 0.13 0.17 0.23 tie bar length q .012 .016 .026 0.30 0.40 0.65 chamfer ch .009 .017 .024 0.24 0.42 0.60 r p a1 a3 ch x 45 b d2 e2 e2 d2 exposed pad width exposed pad length .140 .146 .152 3.55 3.70 3.85 .140 .146 .152 3.55 3.70 3.85 dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per si de. jedec equivalent: pending drawing no. c04-114 mcp23016 ds20090b-page 32 ? 2003 microchip technology inc. 28-lead plastic quad flat no leads package (ml) 6x6 mm body (qfn) (continued) pad width *controlling parameter drawing no. c04-2114 b .009 .011 .014 0.23 0.28 0.35 pitch max units dimension limits p inches .026 bsc min nom max millimeters* min 0.65 bsc nom pad length pad to solder mask l .020 .024 .030 0.50 0.60 0.75 m .005 .006 0.13 0.15 l p m m b package edge solder mask ? 2003 microchip technology inc. ds20090b-page 33 mcp23016 appendix a: revision history revision a (december 2002) original data sheet for mcp23016 device. revision b (september 2003) 1. addition of output low voltage section to table 2-1 in electrical characteristics. 2. addition of output high voltage section to table 2-1 in electrical characteristics. mcp23016 ds20090b-page 34 ? 2003 microchip technology inc. notes: ? 2003 microchip technology inc. ds20090b-page 35 mcp23016 product identification system to order or obtain information (e.g., on pricing or delivery) refer to the factory or the listed sales office. sales and support data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recommended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. part no. x /xx package temperature range device device: mcp23016: 16-bit i 2 c i/o expander temperature range: i= -40 c to +85 c package: sp = plastic dip (300 mil body), 28-lead so = plastic soic, wide (300 mil body), 28-lead ss = plastic soic, (209 mil, 5.30mm), 28-lead ml = plastic quad, flat no leads (qfn), 28-lead examples: a) mcp23016-i/p: industrial temperature, pdip package. a) mcp23016-i/so: industrial temperature, soic package. a) mcp23016-i/ss: industrial temperature, soic package. a) mcp23016-i/ml: industrial temperature, qfn package. mcp23016 ds20090b-page 36 ? 2003 microchip technology inc. notes: ? 2003 microchip technology inc. ds20090b-page 37 information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , mplab, pic, picmicro, picstart, pro mate and powersmart are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. amplab, filterlab, micro id , mxdev, mxlab, picmaster, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. application maestro, dspicdem, dspicdem.net, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, microport, migratable memory, mpasm, mplib, mplink, mpsim, pickit, picdem, picdem.net, powercal, powerinfo, powermate, powertool, rflab, rfpic, select mode, smartsensor, smartshunt, smarttel and total endurance are trademarks of microchip technology incorporated in the u.s.a. and other countries. serialized quick turn programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2003, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification contained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specifications contained in microchip's data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999 and mountain view, california in march 2002. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, non-volatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001 certified. ds20090b-page 38 ? 2003 microchip technology inc. m americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: 480-792-7627 web address: http://www.microchip.com atlanta 3780 mansell road, suite 130 alpharetta, ga 30022 tel: 770-640-0034 fax: 770-640-0307 boston 2 lan drive, suite 120 westford, ma 01886 tel: 978-692-3848 fax: 978-692-3821 chicago 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas 4570 westgrove drive, suite 160 addison, tx 75001 tel: 972-818-7423 fax: 972-818-2924 detroit tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 kokomo 2767 s. albright road kokomo, in 46902 tel: 765-864-8360 fax: 765-864-8387 los angeles 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 phoenix 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7966 fax: 480-792-4338 san jose 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 toronto 6285 northam drive, suite 108 mississauga, ontario l4v 1x5, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific australia suite 22, 41 rawson street epping 2121, nsw australia tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing unit 915 bei hai wan tai bldg. no. 6 chaoyangmen beidajie beijing, 100027, no. china tel: 86-10-85282100 fax: 86-10-85282104 china - chengdu rm. 2401-2402, 24th floor, ming xing financial tower no. 88 tidu street chengdu 610016, china tel: 86-28-86766200 fax: 86-28-86766599 china - fuzhou unit 28f, world trade plaza no. 71 wusi road fuzhou 350001, china tel: 86-591-7503506 fax: 86-591-7503521 china - hong kong sar unit 901-6, tower 2, metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2401-1200 fax: 852-2401-3431 china - shanghai room 701, bldg. b far east international plaza no. 317 xian xia road shanghai, 200051 tel: 86-21-6275-5700 fax: 86-21-6275-5060 china - shenzhen rm. 1812, 18/f, building a, united plaza no. 5022 binhe road, futian district shenzhen 518033, china tel: 86-755-82901380 fax: 86-755-8295-1393 china - shunde room 401, hongjian building no. 2 fengxiangnan road, ronggui town shunde city, guangdong 528303, china tel: 86-765-8395507 fax: 86-765-8395571 china - qingdao rm. b505a, fullhope plaza, no. 12 hong kong central rd. qingdao 266071, china tel: 86-532-5027355 fax: 86-532-5027205 india divyasree chambers 1 floor, wing a (a3/a4) no. 11, o?shaugnessey road bangalore, 560 025, india tel: 91-80-2290061 fax: 91-80-2290062 japan benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa, 222-0033, japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea 135-882 tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 singapore 200 middle road #07-02 prime centre singapore, 188980 tel: 65-6334-8870 fax: 65-6334-8850 taiwan kaohsiung branch 30f - 1 no. 8 min chuan 2nd road kaohsiung 806, taiwan tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan taiwan branch 11f-3, no. 207 tung hua north road taipei, 105, taiwan tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe austria durisolstrasse 2 a-4600 wels austria tel: 43-7242-2244-399 fax: 43-7242-2244-393 denmark regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45-4420-9895 fax: 45-4420-9910 france parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany steinheilstrasse 10 d-85737 ismaning, germany tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy via quasimodo, 12 20025 legnano (mi) milan, italy tel: 39-0331-742611 fax: 39-0331-466781 netherlands p. a. de biesbosch 14 nl-5152 sc drunen, netherlands tel: 31-416-690399 fax: 31-416-690340 united kingdom 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44-118-921-5869 fax: 44-118-921-5820 07/28/03 w orldwide s ales and s ervice |
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